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Experience

Carnegie Mellon University
ServiceNow
Intel
Mentor Graphics
DRDO

Graduate Research Assistant             May – August 2022

Implemented and compared matrix factorization and neural collaborative filtering-based recommendation systems on ThaiBev data, the neural-network based method performed better on all the metrics.
Applied machine learning algorithms on sales and marketing data to helpe increase the engagement on promotions.

Graduate Research Assistant             May – August 2022

Developed critical golang module within a learning management software platform to manage and update the state of domain objects based on time and within-platform events.
Created and debugged a GitHub CI/CD workflow for nightly build and deployment of the platform backend.

Software Development Engineer           March 2021 – January 2022

Led the design of Server Health Auto Remediation Process identifying a problem with the garbage collection process for the puppet servers.
Developed various components of Instance Automation Debugger tool in python which reduced the failed instance debugging time by 30 - 45 minutes.
Communicated across SRE and System Engineering to integrate the Python debugger tool to their workflow, which improved their debugging workflow for failed instances.

Deep Learning R&D Engineer           June 2019 – March 2021

Prototyped and Released Deep learning Chip IP on FPGA and Emulation Platforms.
Created RTL design to make multi-core systems flexible for FPGA.
Increased test coverage of python-based FPGA instance allocation application from 50% to 95%.
Developed automated flow for FPGA IP compilation checks and SW driver level tests using Python and Jenkins. This program added >300 tests, to check the sanity of FPGA IP, prior to this only 5-10 tests were run.

Summer Intern           May – July 2018

Designed and Implemented 8-bit RISC Microprocessor with simple ALU operations using Verilog HDL. Designed simple instruction set to carry out athematic and bitwise operations.

Summer Intern           May – July 2017

Implemented UART communication protocol on FPGA to improve the communication between two microprocessors.